opcode srreg dstreg
010101 sssss ddddd
So if the source register was r7 and the dest register was r9
the bit pattern is
010101 00111 01001
DIV r7, r9
r9 = r9 / r7
(Shaggy...LET R9 = R9 / R7 )
We divide the destination by the source and store the result in the
destination register. This only works on positive numbers. There is
a special hardware register in the RISC chip that controls the
division.This means you can do 32 bit division or 16.16 bit division.
The remander is store in another special hardware register in the
RISC and is 32 bits wide.
ZNC - unaffected
The divide unit does not affect the flags. They remain in the same
state they were BEFORE the DIV was executed.
Cycle 1: Source register read & Destination register read
Cycle 18: Destination register write
There are 1024 variations of the DIV instruction.